1. Field of Invention
The present invention relates to a method of generating timing signals. More particularly, the present invention relates to a method of generating timing signal for controlling a charge-coupled device.
2. Description of Related Art
A number of factors may affect the scanning speed of a scanner or a digital camera. Factors including revolving speed of stepper motor (for a scanner), the number of sensor cells within a charge-coupled device, pixel resolution, the setting of clocking signals during operation are a few of the major ones. In general, these factors are adjusted according to the type of functions desired by a particular scanner or digital camera.
FIG. 1 is a block diagram showing a portion of the circuit inside a conventional scanner. As shown in FIG. 1, intensity of light captured by a charge-coupled device 102 is converted into an analogue signal and then transmitted to an analogue front-end processor 106 inside an application specific integrated circuit 104. The analogue front-end processor 106 is a device for converting analogue signal into digital signal and generating corresponding clocking signals. The analogue front-end processor 106 converts the analogue signal from the charge-coupled device 102 into a digital signal and transmits the digital signal to a digital signal processor 108 for further processing.
The charge-coupled device 102 needs several clocking signals for convening external light intensity to an analogue signal. The required clocking signals are provided by the analogue front-end processor 106. FIG. 2 is a series of timing diagrams showing the clocking signals submitted to a conventional charge-coupled device during operation. The analogue front-end processor 106 provides input timing shift register signals "PHgr"l , "PHgr"2 to the charge-coupled device 102. A cycle in these timing diagrams is actually composed of a plurality of system clock cycles. For example, as shown in FIG. 2, each cycle in the shift register clock cycles "PHgr"l, "PHgr"2 comprises 12 system clock (SystemClk) cycles.
In FIG. 1, light intensity sensed by the sensor cell (not shown) in the charge-coupled device 102 is stored as electric charges within a shift register (not shown) inside the charge-coupled device 102. According to the shift register clock cycles "PHgr"1, "PHgr"2, the shift register transfers the stored electric charges to a pixel processing circuit (not shown) also inside the charge-coupled device 102. When the shift register clock signal "PHgr"1 drops from a xe2x80x98Hxe2x80x99 to a xe2x80x98Lxe2x80x99 logic level and the shift register clock signal "PHgr"2 rises from a xe2x80x98Lxe2x80x99 to a xe2x80x98Hxe2x80x99 logic level as shown in FIG. 2 (the 7th clock cycle), electric charges stored inside another shift register (not shown) are transmitted to the pixel processing circuit. In a similar manner, electric charges stored in any number of shift registers (not shown) are transferred to the pixel processing circuit (not shown) of the charge-coupled device 102.
Reset signal RS and positioning signal CLP are operating cycles for the charge-coupled device 102. In the third clock cycle, the reset signal RS is at a xe2x80x98Lxe2x80x99 logic level (low potential) and the analogue front-end processor 106 generates a reset voltage to flush out the former electric signals within the charge-coupled device 102. In the fourth clock cycle, the reset signal RS changes from xe2x80x98Lxe2x80x99 to xe2x80x98Hxe2x80x99 (a high potential) and the positioning signal CLP changes from a xe2x80x98Hxe2x80x99 to a xe2x80x98Lxe2x80x99 logic level. The analogue front-end processor 106 samples a positioning voltage at time node CDS1. The positioning voltage serves as a reference voltage for the analogue front-end processor 106. In the sixth clock cycle, the positioning signal CLP changes back from xe2x80x98Lxe2x80x99 to xe2x80x98Hxe2x80x99 and the analogue front-end processor 106 samples a charge voltage at time node CDS2. The charge voltage is derived from the charge signal sent from the shift register (not shown) to the analogue front-end processor 106. Voltage difference between the positioning voltage sampled at time CDS1 and the charge voltage sampled at time CDS2 is the brightness value of a first pixel recorded by the charge-coupled device 102 (refer to FIG. 1). The brightness value is registered as an analogue signal.
The phase shift clock signal of a shift register inside a conventional charge-coupled device often has a fixed duty cycle. When a scanner is conducting a low resolution scanning, a faster image processing speed is achieved by using a higher frequency for the phase shift signal. Correspondingly, duty cycle of the analogue front-end processor (time node CDS1 and time node CDS2) is shortened. However, the charge signal from the shift register is submitted in a non-stabilized state. Hence, the signal sampled by the analogue front-end processor is inaccurate and frequency of the pixel processing cycle is increased leading to a high vulnerability to noise interference. Consequently, quality of the scanned image may deteriorate. To produce a high-resolution image, scanning speed of a scanner must slow down. In other words, one must make a compromise between scanning speed and scanning quality.
In addition, the charge-coupled device needs to have different clocking cycles for a scanner capable of scanning different low-resolution images. Therefore, the application specific integrated circuit must be designed anew leading to a slowdown of circuit design turnover.
Accordingly, one object of the present invention is to provide a method of generating clocking signals for a charge-coupled device capable of increasing scanning speed and image quality for a low-resolution scanning. The method is also adaptable to the clocking requirements of different types of charge-coupled devices so that time for designing the scanning circuit of a scanner is reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of generating clocking signals for a charge-coupled device. First, clocking cycle of a shift register signal, a reset signal and a positioning signal related to a charge-coupled device are set. In each cycle of a system clock, for the sampled charge signal that needs to be sampled by the charge-coupled device, cycle of the shift phase register signal corresponding to the charge signal may be extended by an adjustment. For the charge signal that needs to be discarded, cycle of the shift phase register signal corresponding to the charge signal may be shortened by an adjustment. In addition, duration of each cycle for the positioning signal is adjusted in each cycle of the system clock and each cycle of the shift register clock such that the analogue front-end processor can obtain a stable positioning voltage. Furthermore, duration of each cycle for the reset signal is adjusted in each cycle of the system clock and each cycle of the shift register clock corresponding to the charge signal that needs to be discarded. Ultimately, the analogue front-end processor generates a reset voltage to flush away to-be-discarded charge signals. Hence, without changing the internal circuit of an application specific integrated circuit, duty cycle of the shift register signal, the reset signal and the positioning signal may be modified.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.